The JEDEC Solid State Technology Association has announced a preview of new features slated for the upcoming revision of the JESD209-6 LPDDR6 memory standard.
Building upon the foundational standard published in July 2025, JEDEC’s JC-42.6 Subcommittee is steering the technology’s expansion beyond its traditional mobile applications. The planned updates are specifically designed to support data center and accelerated computing workloads that require high-capacity, power-efficient memory platforms.
Key Planned Enhancements to LPDDR6
To accommodate the growing demands of artificial intelligence (AI) and enterprise computing, the next iteration of LPDDR6 will introduce several structural and architectural upgrades:
- Non-Binary Interface Widths and Increased Capacity: The standard will transition from traditional binary widths to include x24, x12, and a new narrower x6 sub-channel mode. This narrower per-die interface allows for more dies per package, significantly increasing memory capacities per component and per channel—a critical requirement for accommodating large AI-scale memory footprints.
- 512 GB Density Capabilities: The updated specification aims to unlock memory densities well beyond the maximum limits of current LPDDR5 and LPDDR5X standards. This expansion targets the high-capacity requirements necessary for advanced AI training and inference tasks.
- Flexible Metadata Carve-Out: To better serve data center environments, the update introduces a flexible approach to metadata management. This feature is designed to minimize disruptions to peak data throughput, allowing operators to balance user capacity against specific reliability and metadata requirements.
Module and Processing Developments
In addition to core architectural changes, JEDEC is actively developing complementary standards to broaden the LPDDR6 ecosystem:
- LPDDR6 SOCAMM2 Module Standard: JEDEC is working on a new module standard based on LPDDR6 to succeed current LPDDR5X SOCAMM2 modules. This development will provide a clear upgrade path while maintaining a compact, serviceable form factor.
- LPDDR6 Processing-in-Memory (PIM): A standard for LPDDR6 PIM is nearing completion. By integrating computational processing capabilities directly within the memory component, LPDDR6 PIM drastically reduces the need to move data between memory and compute units. This architecture is designed to deliver higher inference performance and lower power consumption for both edge and data-center inference workloads, while retaining the inherent energy efficiency of LPDDR designs.
Industry Participation and Status
JEDEC is actively encouraging industry stakeholders to participate in the ongoing development of these standards. Membership grants organizations early access to pre-publication proposals and ongoing projects, including LPDDR6, SOCAMM2, and PIM.
Regarding this, Mian Quddus, JEDEC Board of Directors Chairman, said:
Stay tuned for more details on the next version of LPDDR6 as well as LPDDR6 PIM and LPDDR6 SOCAMM2. The subcommittee continues to evaluate features for inclusion in these standards when they are published.