TSMC unveils 3Dblox 2.0 for enhanced 3D IC design

TSMC has unveiled the 3Dblox 2.0 open standard and highlighted achievements from its Open Innovation Platform (OIP) 3DFabric Alliance during the TSMC 2023 OIP Ecosystem Forum.

TSMC’s 3Dblox 2.0

Last year, TSMC introduced the 3Dblox open standard to simplify 3D IC design in the semiconductor industry. 3Dblox became an essential tool for designing future 3D ICs, thanks to contributions from a vast network of companies.

3Dblox 2.0 empowers designers to explore 3D architecture and evaluate power and thermal aspects early in the design process, all in one place. It also supports chiplet design reuse features, enhancing design efficiency.

Key EDA partners have backed 3Dblox 2.0 to develop solutions for TSMC’s 3DFabric offerings, providing crucial insights for quicker decision-making.

TSMC has established the independent 3Dblox Committee, collaborating with partners like Ansys, Cadence, Siemens, and Synopsys to ensure EDA tool compatibility. Designers can access the latest 3Dblox specs on the 3dblox.org website and explore tool implementation by EDA partners.

3DFabric Alliance Achievements

TSMC’s 3DFabric Alliance has grown significantly in the past year, offering a wide range of solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. The alliance now has 21 partners working together on various initiatives:

Memory Collaboration: TSMC collaborates with leading memory companies like Micron, Samsung Memory, and SK hynix to enhance HBM3 and HBM3e memory capacities, benefiting applications such as generative AI and large language models.

Substrate Collaboration: TSMC partners with IBIDEN and UMTC to simplify substrate design through a Substrate Design Tech file, improving efficiency and productivity. They also focus on design for manufacturing (DFM) enhancements to reduce substrate stress.

Testing Collaboration: TSMC teams up with ATE partners Advantest and Teradyne to tackle 3D testing challenges, aiming to reduce yield loss and enhance chiplet testing efficiency.

Additionally, TSMC is working with Synopsys and ATE partners to achieve a 10x boost in testing productivity and ensure effective interface testing with all design-for-test (DFT) EDA partners.

Speaking at the announcement, Dr. L.C. Lu, TSMC, Vice President of Design and Technology Platform, said:

In light of the industry’s shift towards embracing 3D IC and system-level innovation, the importance of industry-wide collaboration has grown significantly since the inception of OIP 15 years ago. Through our ongoing collaboration with OIP ecosystem partners, we empower customers to leverage TSMC’s cutting-edge process and 3DFabric technologies, enabling them to achieve unprecedented levels of performance and power efficiency for the next generation of artificial intelligence (AI), high-performance computing (HPC), and mobile applications.